The present invention relates to a differential amplifier and, more particularly, to a high-speed wide-band differential amplifier.
FIG. 1 shows a conventional differential amplifier. This differential amplifier has npn transistors Q1 and Q2 as a differential pair. The bases of the npn transistors Q1 and Q2 are connected to input terminals 10 and 12, respectively. The emitter of the npn transistor Q1 is connected to the emitter of the npn transistor Q2 through resistors R1 and R2. The junction between the resistors R1 and R2 is grounded through a constant current source CS. The collectors of the npn transistors Q1 and Q2 are connected to the emitters of other npn transistors Q3 and Q4, respectively. The bases of the npn transistors Q3 and Q4 are commonly connected to a bias voltage source 16. The collectors of the npn transistors Q3 and Q4 are connected to output terminals 18 and 20, respectively. These collectors are also connected to a power source terminal 22 through resistors R3 and R4, respectively.
The differential amplifier shown in FIG. 1 generates an output signal SO at the output terminals 18 and 20 in accordance with an input signal SI. The input signal SI represents the difference between the voltages applied to the input terminals 10 and 12.
FIG. 2 shows the relationship between the power source voltage and the input and output signals SI and SO with respect to the differential amplifier. (VP1 denotes the maximum voltage of the input signal SI; VI1 denotes a voltage amplitude between the maximum and minimum voltages of the input signal SI; VO1 denotes a voltage amplitude between the maximum and minimum voltages of the output signal SO; VCC denotes the potential at a power source terminal 22; VB denotes the output voltage from the bias voltage source 16; and VBE denotes the voltage between the base and emitter of the transistors Q3 and Q4). As is apparent from FIG. 2, different voltage ranges are assigned to voltage variations of the input signal SI and the output signal SO. The following condition is required in order not to saturate the transistors Q1 and Q2 in the amplification of the input signal SI: EQU VP1.ltoreq.VB-VBE (1)
In order to satisfy relation (1), the maximum voltage VP1 of the input signal SI must be limited to a small value. The following condition must be satisfied in order not to saturate the transistors Q3 and Q4 in the amplification of the input signal SI: EQU VO1.ltoreq.VCC-VB (2)
In order to satisfy relations (1) and (2), the voltage amplitude VO1 of the output signal SO must be limited to a small value.
In this differential amplifier, the margin for fluctuation of the power source voltage VCC is small. It is therefore very difficult to maintain a predetermined dynamic range. When the power source voltage VCC is set at a low value, the reliability of this differential amplifier becomes low. However, when the voltage amplitude VI1 of the input signal SI is large, the high-frequency amplification characteristics of this differential amplifier are degraded by a Miller effect due to capacitances between collectors and bases of the transistors Q1 and Q2. In this case, the differential amplifier cannot linearly amplify the input signal SI in a wide frequency range.
FIG. 3 shows an improved conventional differential amplifier. This differential amplifier has npn transistors Q1 and Q2 as a differential pair and pnp transistors Q5 and Q6 as another differential pair. The bases of the transistors Q1 and Q5 are commonly connected to a first input terminal 10, and the bases of the transistors Q2 and Q6 are commonly connected to a second input terminal 12. The input signal SI is supplied across the first and second input terminals 10 and 12. The emitter of the transistor Q1 is connected to the emitter of the transistor Q2 through resistors R1 and R2. The junction between the resistors R1 and R2 is grounded through a constant current source CS2. The emitter of the transistor Q5 is connected to the emitter of the transistor Q6 through resistors R5 and R6. The junction between the resistors R5 and R6 is connected to a power source terminal 22 through a constant current source CS1. The collector of the transistor Q1 is connected to the power source terminal 22, and the collector of the transistor Q5 is grounded. The collector of the npn transistor Q2 is connected to the emitter of the pnp transistor Q7. The base of the transistor Q7 is connected to a first bias voltage source 24, and the emitter thereof is connected to the power source terminal 22 through a resistor R7. The collector of the npn transistor Q6 is connected to the emitter of the npn transistor Q8. The base of the transistor Q8 is connected to the second bias voltage source 26. The emitter of the transistor Q8 is grounded through a resistor R8. The collectors of the transistors Q7 and Q8 are commonly connected to the output terminal 18. The resistor R9 is connected across the output terminals 18 and 20. The output terminal 20 is grounded.
In the differential amplifier shown in FIG. 3, when the input signal SI is supplied across the input terminals 10 and 12, the input signal SI is supplied to the differential pair of the transistors Q1 and Q2 and the differential pair of the transistors Q5 and Q6. The transistors Q5 and Q6 generate an output signal having an opposite phase to that of the output signal from the transistors Q1 and Q2. Therefore, the dynamic range of the collector currents of the transistors Q7 and Q8 can be widened. In this case, in order not to generate an offset voltage at the output terminals of the differential amplifier shown in FIG. 3, the amplification characteristics of the differential pairs must be the same. Therefore, matching between the differential pair constituted by the transistors Q1 and Q2 and the differential pair constituted by the transistors Q5 and Q6, and matching between the constant current sources CS1 and CS2 must be established. In addition, matching between the transistors Q7 and Q8 must be established to obtain identical active load characteristics.
However, it is very difficult to do the above matching. In addition to this disadvantage, the differential amplifier shown in FIG. 3 requires a number of circuit elements, resulting in a high manufacturing cost.